000 01821nam a2200349 a 4500
005 20170415123149.0
008 070717s2007 ne m b a001 0 eng
020 _a0123704901 (pbk. : alk. paper)
_c2880 Bht
020 _a9780123704900 (pbk. : alk. paper)
020 _a0123735904 (CD-ROM)
020 _a9780123735904 (CD-ROM)
040 _aSPU
050 0 0 _aQA 76.9.A73
_bH46C 2007
100 1 _aHennessy, John L.
_991256
245 1 0 _aComputer architecture :
_ba quantitative approach /
_cJohn L. Hennessy, David A. Patterson ; with contributions by Andrea C. Arpaci-Dusseau ... [et al.]
250 _a4th ed.
260 _aAmsterdam :
_bMorgan Kaufmann,
_c2007
300 _a1 v. (various pagings) :
_bill +
_e1 CD-ROM
449 0 _a110800
504 _aIncludes appendix and index
505 0 _aFundamentals of computer design--Instruction-level parallelism and its exploitation--Limits on instruction level parallelism--Multiprocessors and thread-level parallelism--Memory hierarchy design--Storage systems
650 0 _aCOMPUTER ARCHITECTURE
_935896
700 1 _aPatterson, David A.
_991257
700 1 _aArpaci-Dusseau, Andrea C.
_9137436
856 4 1 _3Table of contents only
_uhttp://www.loc.gov/catdir/toc/ecip0618/2006024358.html
856 4 2 _3Publisher description
_uhttp://www.loc.gov/catdir/enhancements/fy0665/2006024358-d.html
910 _aหัวหน้าภาคสถาปัตยฯ
_bบุ๊คเน็ท
_c220307/270607
942 _cGEN
998 _aniparat 0707
_bniparat 0707
999 _c112884